6850 ACIA

Motorola 6850 ACIA

Asynchronous Communications Interface Adapter — a classic UART chip from the late 1970s. Drives serial framing for both RS423/RS232 (when paired with the Serial ULA) and the cassette filing system on the BBC.

Sits on SHEILA &FE08-&FE0F (4 bytes, mirrored across the 8-byte slot).

Registers

Offset	Read	Write
&FE08	Status	Control
&FE09	Receive data	Transmit data

&FE0A-&FE0F mirror the above pair.

Status register (read &FE08)

Bit	Meaning when set
0	RDRF — receive data register full
1	TDRE — transmit data register empty
2	DCD — Data Carrier Detect changed
3	CTS — CTS line is high (not clear to send)
4	FE — framing error (only valid with RDRF)
5	OVRN — receiver overrun (only valid with RDRF)
6	PE — parity error (only valid with RDRF)
7	IRQ — chip is asserting IRQ

The MOS-internal RS423 IRQ handler reads this register on every serial IRQ to figure out which condition triggered (interrupts 6850 path).

Control register (write &FE08)

8 bits:

bit:  7   6   5   4   3   2   1   0
      RIE TX[1]TX[0]WS[2]WS[1]WS[0]CD[1]CD[0]

Bits 1-0 — clock divide

Determines the ratio between the external clock fed to the 6850 and the actual baud rate:

1-0	Effect
00	÷1
01	÷16
10	÷64 — RS423 default; combined with the Serial ULA’s baud-rate select
11	Master reset — clears everything

CFS uses different divide settings to hit 300/1200 baud from the same external clock.

Bits 4-2 — word format

(NAUG §15.3.7 p245)

4 3 2	Word	Parity	Stop
000	7	even	2
001	7	odd	2
010	7	even	1
011	7	odd	1
100	8	—	2
101	8	—	1
110	8	even	1
111	8	odd	1

The traditional default is 8-N-1 (101 = no parity, 1 stop bit).

Bits 6-5 — RTS + transmit IRQ

6 5	RTS	TX IRQ
00	low	disabled
01	low	enabled
10	high	disabled
11	low + break level on TD	disabled

Bit 7 — receive IRQ enable

When set, IRQ fires on any of: receive register full, overrun, DCD transition.

Writing the control register

Use OSBYTE &9C for the canonical Tube-safe path — keeps the MOS shadow copy at the relevant page-2 byte consistent so subsequent serial OS calls don’t trample your settings:

LDA #&9C : LDX #ctrl_byte : LDY #0 : JSR &FFF4

For direct hardware speed, STA &FE08 works but the OS shadow goes stale. If your code keeps ownership (game runs to completion or restarts the OS), that’s fine. If you return to BASIC and another routine touches OSBYTE &9C, your settings get overwritten with the stale shadow value.

OSBYTE &C0 reads the shadow without touching the chip (use for save-and-restore).

TX / RX data

• Transmit: STA &FE09 puts a byte in the transmit register. The chip serialises and ships it. Watch bit 1 (TDRE) of status — set when ready for the next byte.
• Receive: LDA &FE09 pulls the latest received byte. Clears bit 0 (RDRF) of status until the next byte arrives.

IRQ handling

The 6850 IRQ is dispatched first by MOS (before System VIA / User VIA) — see interrupts. MOS dispatches to either the cassette or RS423 driver based on the Serial ULA’s bit 6.

Mask OS handling per source via OSBYTE &E8 (R/W 6850 IRQ bit mask). The bits mirror the status register: setting a bit makes MOS ignore that IRQ source, and the IRQ falls through to IRQ2V for user handling.

Clearing an IRQ

The flag in the status register is cleared by reading the receive register or writing the transmit register. Don’t just clear status — there isn’t a status-clear path. If you mask off MOS handling and don’t read/write the data register in your IRQ2V handler, the IRQ re-fires forever.

See also

• serial-ula — Partner chip (baud rate select, RS423/cassette switch).
• serial — MOS-level serial OS calls.
• interrupts — 6850 IRQ in the MOS dispatch chain.
• memory-map — &FE08-&FE0F in SHEILA.

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This wiki is curated by Claude following the LLM-Wiki methodology — a human curates source documents, the LLM compiles structured cross-linked markdown. Content may contain errors, omissions, or stale claims. For authoritative information refer to the original source documents in the bbc-documents GitHub archive.