6522 VIA — Generic Reference
Two 8-bit bidirectional GPIO ports (A and B), each with 2 control lines (CA1, CA2 / CB1, CB2). Two 16-bit 1 MHz timers (T1, T2). One 8-bit shift register. Interrupt flag + enable registers.
Both BBC VIAs use the same chip; see system-via and user-via for line assignments. Base addresses: System VIA &FE40, User VIA &FE60. Registers repeat every 16 bytes.
Register map
| Reg | Offset | Name | Write function | Read function |
|---|---|---|---|---|
| 0 | +0 | ORB / IRB | Output reg B | Input reg B (output pins read back the register, not the pin) |
| 1 | +1 | ORA / IRA | Output reg A | Input reg A (latched if PCR enables; otherwise live pin) |
| 2 | +2 | DDRB | Data direction B (0=input, 1=output) | same |
| 3 | +3 | DDRA | Data direction A | same |
| 4 | +4 | T1C-L | Loads T1 low-order latch | Reads T1 low-order counter; clears T1 IFR |
| 5 | +5 | T1C-H | Loads T1 high latch; transfers latches → counter; clears T1 IFR | Reads T1 high counter |
| 6 | +6 | T1L-L | Loads T1 low latch (no IFR clear) | Reads T1 low latch |
| 7 | +7 | T1L-H | Loads T1 high latch (no counter transfer) | Reads T1 high latch |
| 8 | +8 | T2C-L | Loads T2 low-order latch | Reads T2 low counter; clears T2 IFR |
| 9 | +9 | T2C-H | Writes T2 high counter; transfers latches; clears T2 IFR | Reads T2 high counter |
| 10 | +A | SR | Shift register | same |
| 11 | +B | ACR | Auxiliary Control Register | same |
| 12 | +C | PCR | Peripheral Control Register | same |
| 13 | +D | IFR | Write 1s to clear flags | Read flag bits |
| 14 | +E | IER | Set/clear enables (see below) | Read enables (bit 7 always reads 1) |
| 15 | +F | ORA/IRA (no handshake) | Output A without CA2 handshake side-effects | Input A without clearing CA1 IRQ |
IRA vs IRB asymmetry
Reading ORB/IRB always returns the value last written to the register, regardless of pin loading. Reading ORA/IRA returns the actual pin level (or latched value if input latching is enabled). For output pins driving a heavy load that distorts the voltage, IRA may read back something different to what was written; IRB will not.
PCR — Peripheral Control Register (reg 12)
| Bits | Field |
|---|---|
| 0 | CA1 active edge: 0=negative, 1=positive |
| 1-3 | CA2 control mode (see below) |
| 4 | CB1 active edge: 0=negative, 1=positive |
| 5-7 | CB2 control mode (see below) |
CA2 / CB2 control modes (bits 1-3 / 5-7):
| Code | Function |
|---|---|
| 000 | Input, IRQ on negative edge, cleared by R/W ORA/ORB |
| 001 | Independent IRQ, negative edge (cleared only by writing 1 to IFR) |
| 010 | Input, IRQ on positive edge, cleared by R/W ORA/ORB |
| 011 | Independent IRQ, positive edge |
| 100 | Handshake output |
| 101 | Pulse output |
| 110 | Low output |
| 111 | High output |
ACR — Auxiliary Control Register (reg 11)
| Bits | Field |
|---|---|
| 0 | PA input latch: 0=disable, 1=enable (latched on CA1 edge) |
| 1 | PB input latch |
| 2-4 | Shift register mode (8 modes) |
| 5 | T2 mode: 0=interval timer, 1=count PB6 pulses |
| 6 | T1 mode: 0=one-shot, 1=continuous |
| 7 | T1 PB7 output: 0=disabled, 1=toggles PB7 on each timeout |
Combined bit 6, bit 7:
| 6 | 7 | T1 behaviour |
|---|---|---|
| 0 | 0 | One-shot interrupt, no PB7 |
| 0 | 1 | One-shot interrupt + PB7 pulse (low during count) |
| 1 | 0 | Free-run interrupts, no PB7 |
| 1 | 1 | Free-run interrupts + PB7 square wave |
IFR — Interrupt Flag Register (reg 13)
| Bit | Source |
|---|---|
| 0 | CA2 active edge |
| 1 | CA1 active edge |
| 2 | Shift register completed 8 bits |
| 3 | CB2 active edge |
| 4 | CB1 active edge |
| 5 | T2 timeout |
| 6 | T1 timeout |
| 7 | Any enabled IRQ asserting — read-only summary |
Write 1 to any bit (except 7) to clear that flag. Bit 7 cannot be written to clear; it follows the OR of (flags AND enables).
IER — Interrupt Enable Register (reg 14)
Unusual write protocol:
- Write
bit 7 = 0: clear the enable bits where bits 0-6 are1; other enables unchanged. - Write
bit 7 = 1: set the enable bits where bits 0-6 are1; other enables unchanged.
Examples:
LDA #&7F : STA IER→ disables all interrupts.LDA #&82 : STA IER→ enables CA1 only.LDA #&02 : STA IER→ disables CA1 only.
Reading IER returns bit 7 = 1 always; bits 0-6 are the current enable state.
Timers — quick reference
T1 timeout = (N+2) × 1 µs where N is the 16-bit loaded value. T1 latches survive timeout; in free-run mode the counter reloads from the latches and continues.
T2 = interval timer (one-shot, fires once per write to T2C-H) or PB6 pulse counter (ACR bit 5 = 1). No PB7 output.
Both timers can be re-triggered by writing T1C-H / T2C-H again — useful to extend a count before it fires.
See via-timers for usage patterns (raster timing, audio, periodic IRQs).
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